Circuit simulation for semiconductor devices has increasingly gained importance in recent years.
In this respect, in the semiconductor devices in the related art, the gate capacitance and the wiring capacitance of a MOS-FET transistor have great effect, while the capacitance near the MOS-FET transistor has only negligible effect.
As the miniaturization advances, it causes a problem that measured values of the circuit simulation and the silicon device do not match each other. For example, a simulation error at a frequency more than 10% occurs in a ring oscillator of a digital circuit with 40 nm technology.
The major cause thereof is an error of the simulation accuracy of the capacitance near the MOS-FET transistor.
The characteristics of the capacitance near the MOS-FET transistor are relatively large, and the effect on the circuit frequency becomes large. Particularly, the significant characteristics in circuit design are a gate fringe capacitance, a gate overlap capacitance, and a gate contact plug capacitance, included in the capacitance near the MOS-FET transistor.
At this point, Japanese Unexamined Patent Publication No. 2011-129615 discloses a technique for extracting the gate overlap capacitance as a capacitance of an overlapped part of the gate, the source, and the drain.
A fixed value is generally used for the gate fringe capacitance as one capacitance near the MOS-FET transistor. It does not guarantee circuit simulation with high accuracy.